1. Field of the Invention
The present invention is directed to a method for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell.
2. Description of the Related Art
Memory cells with trench capacitors are utilized in integrated circuits (ICs) such as random-access memories (RAMs), dynamic RAMs (DRAMs) and synchronous DRAMs (SDRAMs). The ICs typically employ capacitors for the purpose of charge storage. In dynamic write/read memories with random access (DRAMs), for example, the charge status of the capacitor is thus used for the representation of a data bit.
Over and above this, a DRAM memory cell also comprises a xe2x80x9cselection transistorxe2x80x9d that is electrically conductively connected to the capacitor. Typically, the selection transistor is a MOS transistor, i.e., it comprises a source region and a drain region that are separated from one another by a channel zone. A gate electrode is arranged over the channel zone via which the flow of current in the channel can be controlled. For driving the memory cell, one of the source/drain regions (S/D regions) is connected to the bit line, and the gate electrode is connected to the word line of the memory. The other S/D region is connected to the capacitor.
The continued striving for miniaturization of the memory devices requires the design of DRAMs with a higher density and smaller characteristic quantity, i.e., a smaller memory cell area. This could be enabled by employing smaller components, i.e., smaller capacitors. Due to a miniaturization of the capacitors, however, their storage capacity is also reduced, which has a negative influence on the function of the memory cell: first, the required dependability in the readout of the stored value can no longer be guaranteed; and second, the refresh frequency in DRAMs must be increased.
One solution of this problem is offered by the trench capacitor, where the capacitor area is vertically arranged in a trench in the substrate. This arrangement allows a relatively large capacitor area, i.e., an adequately large capacity, given a simultaneously slight surface requirement. For manufacturing a trench capacitor, a trench is first etched into a substrate. For forming the first capacitor electrode, for example, a dopant is then introduced into the substrate material surrounding the trench wall. The trench wall is then lined with a dielectric, whereby ONO is employed, for example, as dielectric. The trench is subsequently filled up with an electrically conductive filler material. Preferably, an insulator collar that prevents a leakage current to the first electrode is formed in an upper region of the trench insulator. Methods for manufacturing trench capacitors are disclosed, for example, by European Patent Documents EP 0 491 976 B1 and EP 0 971 414 A1.
For manufacturing a memory cell, the capacitor must ultimately also be connected to an S/D region of the transistor, which can occur, for example, via a strap contact. The strap contact is typically fashioned as a buried strap contact (xe2x80x9cburied strapxe2x80x9d), i.e., the contact is produced under the upper substrate surface, since this arrangement has the advantage that it requires less area than a strap contact lying at the surface. A buried strap contact thus facilitates a miniaturization of the memory cell.
In the manufacture of such a buried strap contact, a bridge is generated on the filler material of the second electrode in the trench, this bridge being typically composed of polysilicon and representing a part of the strap contact. A doped diffusion region that extends up to an S/D region of the transistor is fashioned in that region of the monocrystalline silicon adjacent to the bridge. Together, the diffusion region and the bridge form the strap contact that produces an electrically conductive connection between the second capacitor electrode and the S/D region of the transistor. Methods for manufacturing such buried strap contacts are disclosed, for example, by European Patent Documents EP 0 939 430 A2, EP 0 939 435 A1 and EP 0 971 414 A1.
As mentioned above, highly doped polysilicon is typically employed for the electrically conductive filler material. For example, As is suitable as dopant, this being introduced into the polysilicon in a concentration of 1019 through 1020 cmxe2x88x923. On the basis of a temperature-controlled diffusion step, the dopant can diffuse from the filler material into the polysilicon of the bridge and from the latter into the adjacent monocrystalline silicon of the substrate and thus form a diffusion zone that has an adequately high electrical conductivity and produces the electrical contact between the capacitor and the transistor.
So that a satisfactory contact is produced between the trench capacitor and the transistor, it is necessary that the diffusion zone is generated in an exactly defined region between the bridge and the gate electrode. After the diffusion zone and the bridge have been structured in the substrate, the gate electrode is usually generated on the substrate via a photolithographic process for this purpose. I.e., after the deposition of the layers forming the gate stack, a photoresist layer is deposited on the layers, exposed through a mask, and subsequently developed. The gate electrode is then structured via an appropriate etching.
This type of positioning of the gate electrode relative to the diffusion zone and the bridge, however, is affected by pronounced positional tolerances, which can lead to too great an overlap between the diffusion zone and the gate electrode and, thus, to great fluctuations in the effective channel length of the selection transistor, as a result of which its function can be degraded.
It is therefore an object of the present invention to provide an efficient and effective method for the manufacture of a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. A further object of the present invention is to provide an efficient and effective manufacturing method that can be easily integrated into an existing manufacturing process. Over and above this, an object of the present invention is to provide an efficient and effective manufacturing method that allows a miniaturization of the memory cell without negatively influencing the performance of the memory cell.
Inventively, a method for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell, is provided that comprises:
a) a trench capacitor is generated in a substrate, the trench capacitor comprising a lower region filled with a first doped filler material having a first width and comprising an open, unfilled region adjacent thereto, whereby the unfilled region comprises sidewalls and a floor formed by the first, doped filler material;
b) the unfilled region of the trench capacitor is filled with essentially monocrystalline silicon;
c) gate paths are generated on the substrate surface;
d) for generating the buried strap contact, a contact trench having a second width is etched at least down to the depth of the floor formed by the first doped filler material, whereby the gate paths form at least part of the mask utilized for etching the contact trench;
e) a second filler material is deposited in the contact trench for forming a buried bridge as part of the buried strap contact, whereby the buried bridge is in direct contact with the first doped filler material; and
f) at least one thermal treatment is implemented in order to generate a diffusion region as part of the buried strap contact.
The inventive method makes it possible to generate the diffusion region, which produces the contact between the trench capacitor and the selection transistor, with a higher positional precision and without an additional photolithographic step. Accordingly, the process stability is enhanced and, thus, a better yield is achieved in the overall process of the memory cell manufacture. The spacing between gate electrode and bridge is exactly defined in that the gate paths, particularly the gate path of the selection transistor of the memory cell, form at least a part of the mask for the definition of the bridge of the strap contact. Accordingly, the diffusion region to be generated via the thermal treatment and the effective channel length of the transistor can be precisely set in a simple way.